Experiencing the Milk-V Megrez RISC-V AI PC

1. Introduction: A Leap into RISC-V 64-bit

The world of computing is currently defined by a handful of Instruction Set Architectures (ISAs). While x86 and ARM have long been the pillars of desktop/server and mobile/embedded computing, an exciting new player is rapidly gaining ground: RISC-V. RISC-V offers an open, customizable, and future-proof foundation for hardware innovation. Today, we’re diving deep into an exciting piece of hardware that brings this potential to life: the Milk-V Megrez RISC-V AI PC.

The Megrez isn’t just another single-board computer; it’s a powerful 64-bit RISC-V development platform delivered in a practical Mini-ITX form factor. This machine represents a critical milestone in making high-performance RISC-V systems accessible to developers, AI enthusiasts, and researchers.

2. Acknowledgment & Hardware Deep Dive

This opportunity to test and develop on cutting-edge RISC-V hardware was made possible by the community. We extend our sincere gratitude to Greg Sterling of RISC-V International and the team behind the RISC-V International for their support. A special thanks also goes to Milk-V for providing the Milk-V Megrez board for testing/development.

The Megrez specifications provide the muscle for ambitious projects:

3. Core Testing: OS Stability and Virtualization

My primary goal was to validate the Megrez for Desktop computing and SME (Small and Medium Enterprise) server solutions, leveraging the emerging official support for RISC-V.

• Initial OS Setup: Thanks to Milk-V’s excellent documentation, I started with RockOS (a Debian Trixie-based distribution with Linux Kernel 6.6.88. While the desktop experience was functional for daily/basic tasks, the real focus began with server-centric testing.

• LXC Containerization: I successfully deployed pure, upstream images of Debian 13 (Trixie) and Ubuntu 24.04 LTS via LXC (Linux Containers). This confirmed the official RISC-V repository maturity and allowed stable resource isolation for testing.

• Full Virtualization (QEMU): Utilizing QEMU and the Cockpit web UI (with cockpit-machines), I created full Virtual Machines to test operating system images. This validated the core’s virtualization capabilities and its readiness for sophisticated server management tasks, moving beyond simple containers.

• SME Workloads: The board efficiently ran a complete web service stack (e.g., Web Server, PHP, MariaDB) enabling stable tests of applications like WordPress and open-source ERP systems. The 32GB of LPDDR5 was transformative for database caching and handling multi-service loads.

4. Pushing the Envelope: Kernel Hacking and AI Acceleration

This phase focused on the platform’s high-level development potential:

• NPU Integration for LLMs: I tested the dedicated NPU (19.95 TOPS@INT8) for LLM service and found the sample performance to be quite impressive. Crucially, fine-tuning of an LLM worked, demonstrating that the full AI toolchain is viable on this hardware. This is a massive step for on-device AI development on RISC-V.

• Linux Kernel Compilation: As a personal challenge, I compiled Linux Kernel 6.6.108 from source. This involved significant patch work, but achieving a successful boot, even once, was a major testament to the core’s reliability and the growing maturity of the native RISC-V toolchain.

5. Conclusion & Future Roadmap 🚀

Over the last few months, the Milk-V Megrez has proven that high-performance, 64-bit RISC-V is no longer a niche concept; it’s a stable platform ready for serious work.

My experience across virtualization, web applications, and kernel development has given me the confidence to offer solutions built on this architecture. The future of testing is focused on the Megrez’s long-term utility:

Milk-V Megrez Next Steps:

• Server Ecosystem: Testing for Storage Gateway, Nextcloud, Mail Server, and traditional NFS/SMB server roles.
• Modern Applications: Checking Rust-based coding and applications, AI streaming, and model building.
• Kernel Upstream Work: I am still working on getting Linux Kernel 6.12 and 6.18 running to check out the latest upstream changes.

Broader RISC-V Ecosystem Goal:

• Vector Performance: Future testing will specifically target the performance of the RISC-V Vector Extension (RVV), exploring its impact on computationally intensive workloads as compatible hardware and software tools become more prevalent.

I will be posting all my scripts and technical quick tips notes used during these tests in my GitHub repository for the community.